Elenco Electronics MO-1251 Manual do Utilizador descarregar pdf (Página 58)

100

71N

5-15V

161

1ouT -

fn0

CLK

40178 CARRY

OUT

RESET

CLK ENABLE

115

113

FIG. 3-A

4017B CONNECTED

as a decade

counter

divider.

fIN

IC4-a

4001B

CLK

f11111

ENABLE line, and is therefore

not

both-

ered

by a trigger signal

with a slow

rise time.

An additional CARRY

OUT

signal (pin 12) completes

one cycle

for every

ten clock cycles

and, as

we'll see, can be used

to clock addi-

tional

4017B's in a multi -decade

rip-

ple

counter.

Decade

circuits

Figure 3 shows

the 4017B con-

nected as a decade

divider,

where the

output frequency

is 1 /10th the

input

+5-15V

ICI

40178

CARRY

OUT

CLK

RESET

ENABLE

1C2

40116

CLK

IC4

four,

100

:4001B

CARRY

OUT

CLK

RESET

ENABLE

113

IC4-c

'/<

4001B

12 14

IC3

40178

CARRY

CLK

OUT

CLK

RESET ENABLE

15 113

fliir1000

IC4-d

40mB

FIG. 4 -ANY

NUMBER OF

4017B's can

be cascaded to

make a

multi- decade

divider.

Outputs

should

be buffered

using a

4001B CMOS

INVERTER gate.

CLOCK

INPUT

+5-15V

1111171

RESET

CLK

4017.

CLK- EI ABLE

DECODED

OUTPUTS

1 2

3 4

5 6

8 9

3 2

7 10

Nth OUTPUT

5 6

FIG. 5 -THE

4017B AS

A DIVIDE -BY

-N

COUNTER.

This circuit

set

for divide -

by-5 operation.

frequency.

The IC is always

asserted

because

RESET and CLOCK

ENABLE are

grounded. The output

is taken from

the CARRY OUT, while

the DECODED OUT-

PUTS are ignored.

Figure

4 shows how to cascade

4017B counters to divide

theflN clock

frequency by 10,

100,

and

1000. The

CARRY

OUT of each counter

is used as

the clock

input to the following

IC.

Notice that all

fOuTPUTS

are buffered

via

simple CMOS inverters

(made

from

4001B

NOR gates);

that ensures

CLOCK

INPUT

ICI -b

Y. 4001B

IC1-d

Y. 40018

1--

411-

+5-15V

16f

14 CLK

RESET

ICI

4017B

CLK ENABLE

DECODED

OUTPUTS

1 2

5 6

3 2

Nth

OUTPUT

FIG. 6-A DIVIDE -BY

-N

COUNTER

USING

A 4017B.

The extra

logic gates

ensure

minimum

reset

pulse- width.

stopped

by setting the CLOCK

ENABLE

(pin 13) high. Furthermore,

the IC has

a built -in Schmitt

trigger on

its CLOCK

that

output loading

does not

degrade

the

pulse's rise time.

For example,

using

a 1 -MHz crystal

oscillator

as a

+5-15V . T

. -Slo

R1 1

RESET

100K =

16 5

RESET

CLOCK

INPUT

CLK

ICI

CLK ENABLE

40178

ONO

DECODED

OUTPUTS

6 7

21 41

71101

l 1

51 61 91

FIG.

7 -THE 4017B CONNECTED

for

se-

quence-

and -stop action.

clock, then a 100 kHz, 10 kHz, and

kHz frequency can be generated.

Figure 5 shows

how

to connect

the

4017B as a divide -by -N

counter

(where N = any integer from 2 to 9).

A divide -by -N counter

(or Mod -N

counter)

has its "Nth" DECODED OUT-

PUT hard -wired back to the RESET.

The

counter

then

cleared to its zero cou-

nt (a high

on pin DECODE OUTPUT 0) on

the arrival of the "Nth" clock

pulse.

What

could

happen if the divide -

by-5 counter, in Fig. 5, used

a clock

signal having an extremely

slow rise

time?

The RESET could be triggered

high and then low

(by

the

DECODED

OUTPUT 5)

while

the

slowly rising

clock is still rising.

The DECODED OUT-

PUT 0 is reset high, but is then

imme-

diately

clocked again by the

remaining

positive edge of the

rising

clock

-causing the DECODED OUTPUT

to shift to the next position.

Now let's

design a circuit

to avoid that problem.

Figure 6 shows

a slightly more

re-

liable

version

the divide -by -N

counter.

Logic gates

control the

RESET

operation

via ICI -a to ICI -d, (IC1

-a

and IC1 -b form

a NOR flip -flop).

Here

the

RESET command

is latched high

the arrival

of the

"Nth"

clock

pulse,

only

while

the

clock pulse remains

high, but is removed

automatically

when

the clock

pulse goes low again.

Those extra gates

ensures a

minimum

RESET

pulse

width

(for a given

clock

rise time),

which stabilizes counter

operation.

The

4017B is particularly

useful for

whole range of

"sequencer"

ap-

plications,

where the DECODED

OUT-

PUTS

can drive

LED displays,

relays,

sound generators.

Sometimes

it's desirable to

count

up to a predetermined

number and

then

stop. Figure 7

shows a 4017B

wired for

that

type of operation.

The

counter

will stop

when

its CLOCK

EN-

ABLE pin is driven

high by DECODED

OUTPUT

9; moreover, the counter

can

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 99 100

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